@ignitionnet so you would say that a lot of it is done by asics, not just the low level stuff, rather than by CPUs and normal software? There is a chapter on silicon exactly this subject, in Golden, Dedieu eg al vol 2 but that was written ten years ago, although it does mention vectoring theory so they did very well, but anyway, it cannot describe 2018 hardware. From what I read about G.INP, having looked at the standards doc, I would myself have done it in software, given a decent CPU, but then that's what software people do who don't speak hardware. To a farmer everything looks like a cow, what is it they say?
I kind of assumed that more could be taken on by CPUs nowadays if vector instructions are a useful aid as they have got wider and more capable in some CPUs but possibly not in the low power cheap cores that eg Broadcom might use in a modem. But otherwise CPUs have not got any faster in the last few years. The odd program that Inhave written recently do x64 has got dramatically faster on a post 2012 Intel CPU because of the arrival of certain new special instructions which were wisely picked to plug a hole, a common performance nightmare idiom. Things like POPCNT and LZCNT or whatever they’re called and the new instruction to pack sparse group of bits together, gone blank. Some years back the number of instructions that can be scheduled in parallel with out-of-order has improved a bit further. But more recently, unless you hit one of those special situations where one of those special-case instructions gives a massive boost in an inner loop in a leaf function then you don't see any big improvement over the last few years, not unless you actually can exploit multiple cores, which is a pain, dangerous, not always applicable and so on.
But anyway, the modem developers perhaps really do not want the cost and power consumption of some beast like a modern x86 CPU, what with its instruction set translation to micro ops and out-of-order and all that stuff which eats power, while some of it is only there because backwards compatibility with a 1985, or even 1977, old instruction set.
Quite agree with you about the tail off. They can only maintain that Moore's law is holding up if they count in the multiple cores and maybe also the parallelism of SIMD vector instructions too.