The line do cards support vectoring, wastage occurs as you say due to how the cable has to be laid out in that you cant have different feeders on the same line card.
I had previously wondered why their 1st example only used 48 ports. I hadnt seen that IVE1000 link before and
if that is the chip that is used on the VTU-C64's then it now makes perfect sense why ECI used 48 ports for the vectoring at line card level for their example. ie its a limitation of the chip because it cant cope with vectoring more than 48 ports on the card.
The way I read it is:
The VINAX Vectoring chipset supports all variations of energy efficient, vectored (DSM-L3) VDSL2 aggregation systems. It consists of an Integrated Vector Engine IVE1000 optimized coprocessor
and the Vinax V3 chip set.
This is the chipset on the VTU-C64 line card, which can do line card level vectoring
One VINAXTM IVE1000 device allows full cancellation for up to 48 ports in profiles 17/12/8 and up to 32 ports in profile 30.When connected to a standard compliant CPE device such as the XWAY™
VRX200, this combination allows the implementation of a complete end-to-end vectoring solution
To get more out of it connect to a VRX200 to do shelf level vectoring
supports up to 384 VDSL2 ports by cascading multiple IVE1000 devicesHere the Vectoring module is doing the hardwork and performing multiple vectoring regardless which feeder is connected to which line card port and able to keep track of things and no port wastage.
Kind of like how a motherboard may have a basic onboard graphics, but to do anything decent you need a proper Graphics card.
What's labelling those 0xb204 bytes as the "chipset version"? The G.994.1 PDF just says they are "vendor-specific information". It does not say they indicate the "chipset version".
I dont have a clue. I was looking the other week and googling FPGA & (iirc) Vendor id, didn't provide any definite answers but started to give an inkling. I really cant recall what I did find where, but I think it was something relating to bonding, so in otherwords use FPGA to set the chipset to do bonding or add a module to do bonding and that number could change. I think it implied by changing the gates then you could end up with another number, but Im unsure if that is under the CP control or if they are preset by the vendor. There was also something about it depends if was open or closed id but I think that may have come from someone was using FPGA to build their own version of a graphics card.
I really dont know enough about FPGA, but I am beginning to suspect that if they change something major using FPGA then you will get a new number if the manufacturer has pre-registered that configuration it as say IFN[hex].
Its a while since I looked and I've got to go out in a mo, you may find something more definite in that area. Dont take what I said above as gospel Im only telling you so where I started looking and about as far as I got... and I may have remembered wrong.
Unless someone else knows more about FPGA and how it works than I do... and that wont be hard since I know practically zilch other than you can use it to make remote changes to the line card.
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Topic: Huawei DSLAM - Chipset version changed - Vectoring? (Read 28918 times)