I can't answer your query regarding the e-mail messages but I am looking at the last 48 hours worth of statistics for your circuit.
The SNRM plot shows that two resynchronisation events occurred, the first at 1126 hours (on 19th January) and the second at 2030 hours (also 19th January). Between those two events there does not appear to be any data available to plot.
The SNRM, CRCs and FECs plots all look reasonable (ignoring the data gap).
The Hlog plot shows nothing to be concerned about, the physical metallic pathway is seen as perfectly reasonable. However the QLN plot seems to indicate that you have significant crosstalk affecting the first two DS bands. It is clear that a significant power cut back has been applied in the first DS band, the reason being so as not to "drown out" the ADSL signals on circuits which also share the same D-side cable binder as your VDSL2 circuit.